Peripheral,BaseAddr,Register,Offset,Field,BitOffset,BitWidth
TMR2,0x40000000,CTRL1,0x0,PMEN,10,1
TMR2,0x40000000,CTRL1,0x0,CLKDIV,8,2
TMR2,0x40000000,CTRL1,0x0,PRBEN,7,1
TMR2,0x40000000,CTRL1,0x0,TWCMSEL,5,2
TMR2,0x40000000,CTRL1,0x0,OWCDIR,4,1
TMR2,0x40000000,CTRL1,0x0,OCMEN,3,1
TMR2,0x40000000,CTRL1,0x0,OVFS,2,1
TMR2,0x40000000,CTRL1,0x0,OVFEN,1,1
TMR2,0x40000000,CTRL1,0x0,TMREN,0,1
TMR2,0x40000000,CTRL2,0x4,C1INSEL,7,1
TMR2,0x40000000,CTRL2,0x4,PTOS,4,3
TMR2,0x40000000,CTRL2,0x4,DRS,3,1
TMR2,0x40000000,STCTRL,0x8,ESP,15,1
TMR2,0x40000000,STCTRL,0x8,ECMBEN,14,1
TMR2,0x40000000,STCTRL,0x8,ESDIV,12,2
TMR2,0x40000000,STCTRL,0x8,ESF,8,4
TMR2,0x40000000,STCTRL,0x8,STS,7,1
TMR2,0x40000000,STCTRL,0x8,STIS,4,3
TMR2,0x40000000,STCTRL,0x8,SMSEL,0,3
TMR2,0x40000000,IDEN,0xC,TDEN,14,1
TMR2,0x40000000,IDEN,0xC,C4DEN,12,1
TMR2,0x40000000,IDEN,0xC,C3DEN,11,1
TMR2,0x40000000,IDEN,0xC,C2DEN,10,1
TMR2,0x40000000,IDEN,0xC,C1DEN,9,1
TMR2,0x40000000,IDEN,0xC,OVFDEN,8,1
TMR2,0x40000000,IDEN,0xC,TIEN,6,1
TMR2,0x40000000,IDEN,0xC,C4IEN,4,1
TMR2,0x40000000,IDEN,0xC,C3IEN,3,1
TMR2,0x40000000,IDEN,0xC,C2IEN,2,1
TMR2,0x40000000,IDEN,0xC,C1IEN,1,1
TMR2,0x40000000,IDEN,0xC,OVFIEN,0,1
TMR2,0x40000000,ISTS,0x10,C4RF,12,1
TMR2,0x40000000,ISTS,0x10,C3RF,11,1
TMR2,0x40000000,ISTS,0x10,C2RF,10,1
TMR2,0x40000000,ISTS,0x10,C1RF,9,1
TMR2,0x40000000,ISTS,0x10,TRGIF,6,1
TMR2,0x40000000,ISTS,0x10,C4IF,4,1
TMR2,0x40000000,ISTS,0x10,C3IF,3,1
TMR2,0x40000000,ISTS,0x10,C2IF,2,1
TMR2,0x40000000,ISTS,0x10,C1IF,1,1
TMR2,0x40000000,ISTS,0x10,OVFIF,0,1
TMR2,0x40000000,SWEVT,0x14,TRGSWTR,6,1
TMR2,0x40000000,SWEVT,0x14,C4SWTR,4,1
TMR2,0x40000000,SWEVT,0x14,C3SWTR,3,1
TMR2,0x40000000,SWEVT,0x14,C2SWTR,2,1
TMR2,0x40000000,SWEVT,0x14,C1SWTR,1,1
TMR2,0x40000000,SWEVT,0x14,OVFSWTR,0,1
TMR2,0x40000000,CM1_OUTPUT,0x18,C2OSEN,15,1
TMR2,0x40000000,CM1_OUTPUT,0x18,C2OCTRL,12,3
TMR2,0x40000000,CM1_OUTPUT,0x18,C2OBEN,11,1
TMR2,0x40000000,CM1_OUTPUT,0x18,C2OIEN,10,1
TMR2,0x40000000,CM1_OUTPUT,0x18,C2C,8,2
TMR2,0x40000000,CM1_OUTPUT,0x18,C1OSEN,7,1
TMR2,0x40000000,CM1_OUTPUT,0x18,C1OCTRL,4,3
TMR2,0x40000000,CM1_OUTPUT,0x18,C1OBEN,3,1
TMR2,0x40000000,CM1_OUTPUT,0x18,C1OIEN,2,1
TMR2,0x40000000,CM1_OUTPUT,0x18,C1C,0,2
TMR2,0x40000000,CM1_INPUT,0x18,C2DF,12,4
TMR2,0x40000000,CM1_INPUT,0x18,C2IDIV,10,2
TMR2,0x40000000,CM1_INPUT,0x18,C2C,8,2
TMR2,0x40000000,CM1_INPUT,0x18,C1DF,4,4
TMR2,0x40000000,CM1_INPUT,0x18,C1IDIV,2,2
TMR2,0x40000000,CM1_INPUT,0x18,C1C,0,2
TMR2,0x40000000,CM2_OUTPUT,0x1C,C4OSEN,15,1
TMR2,0x40000000,CM2_OUTPUT,0x1C,C4OCTRL,12,3
TMR2,0x40000000,CM2_OUTPUT,0x1C,C4OBEN,11,1
TMR2,0x40000000,CM2_OUTPUT,0x1C,C4OIEN,10,1
TMR2,0x40000000,CM2_OUTPUT,0x1C,C4C,8,2
TMR2,0x40000000,CM2_OUTPUT,0x1C,C3OSEN,7,1
TMR2,0x40000000,CM2_OUTPUT,0x1C,C3OCTRL,4,3
TMR2,0x40000000,CM2_OUTPUT,0x1C,C3OBEN,3,1
TMR2,0x40000000,CM2_OUTPUT,0x1C,C3OIEN,2,1
TMR2,0x40000000,CM2_OUTPUT,0x1C,C3C,0,2
TMR2,0x40000000,CM2_INPUT,0x1C,C4DF,12,4
TMR2,0x40000000,CM2_INPUT,0x1C,C4IDIV,10,2
TMR2,0x40000000,CM2_INPUT,0x1C,C4C,8,2
TMR2,0x40000000,CM2_INPUT,0x1C,C3DF,4,4
TMR2,0x40000000,CM2_INPUT,0x1C,C3IDIV,2,2
TMR2,0x40000000,CM2_INPUT,0x1C,C3C,0,2
TMR2,0x40000000,CCTRL,0x20,C4P,13,1
TMR2,0x40000000,CCTRL,0x20,C4EN,12,1
TMR2,0x40000000,CCTRL,0x20,C3P,9,1
TMR2,0x40000000,CCTRL,0x20,C3EN,8,1
TMR2,0x40000000,CCTRL,0x20,C2P,5,1
TMR2,0x40000000,CCTRL,0x20,C2EN,4,1
TMR2,0x40000000,CCTRL,0x20,C1P,1,1
TMR2,0x40000000,CCTRL,0x20,C1EN,0,1
TMR2,0x40000000,CVAL,0x24,CVAL,0,32
TMR2,0x40000000,DIV,0x28,DIV,0,16
TMR2,0x40000000,PR,0x2C,PR,0,32
TMR2,0x40000000,C1DT,0x34,C1DT,0,32
TMR2,0x40000000,C2DT,0x38,C2DT,0,32
TMR2,0x40000000,C3DT,0x3C,C3DT,0,32
TMR2,0x40000000,C4DT,0x40,C4DT,0,32
TMR2,0x40000000,DMACTRL,0x48,DTB,8,5
TMR2,0x40000000,DMACTRL,0x48,ADDR,0,5
TMR2,0x40000000,DMADT,0x4C,DMADT,0,16
TMR2,0x40000000,TMR2_RMP,0x50,TMR2_CH1_IRMP,10,2